After quite some time, I am finally starting to check my 4002 signal generator in-depth. The first thing I want to do before really starting this project is to get a good idea of the system layout, hence the “part 0” thing above. I will link from here to the different components as I wriggle through the unit and check them. As there is no service documentation freely available, I will go deeper into critical parts of the circuit along the way.
This will also help me simplify things later when trying to figure out which line went where, if things go wrong.
Clock source (Decade stage)
Contained in the bottom RF block, consists of a styrofoam-encapsulated 10.000(00…) MHz oven-controlled precision oscillator and some clock distribution buffering. This part sources the main TTL clock which is also available on the backside ports as an instrument reference. The picture shows the whole top side of the module block, but the actual OCXO and distributor PCB are on the right.
There are three additional circuits in this module: The 10 MHz TTL buffering and switchover for external references, a 10.7 MHz IF generator (PLL+VCO+Mixer) and another phaselocked VCO for a derived widerange signal (49.3-70.7 MHz according to the marking) which is used to fine-tune the RF synthesis stage.